Parasitic extraction challenges and solutions for 5G IC design

To fulfill the performance promise of 5G while ensuring 5G IC designs can be successfully manufactured in commercial quantities, designers of 5G chips and networks need accurate, automated parasitic extraction and simulation of 5G IC layouts so they can reduce the impact of parasitics by optimizing their chips before manufacturing. In 5G design, parasitic extraction EDA tools help engineers validate that their chip designs can handle the high demand of a 5G network and deliver the designed circuit performance by enabling design teams to accurately account for the impact of parasitics on complex components such as FD-SOI transistors and MIM/MOM capacitors, as well as the high frequencies used in these designs.

Multiple integrated parasitic extraction techniques in one EDA tool accurately and efficiently extract all parasitics in 5G IC design layouts

The Calibre xACT platform, which provides fully-integrated rule-based and field solver parasitic extraction, automatically employs the applicable extraction technology to accurately extract all parasitics in 5G IC design components and networks. Support for FD-SOI processes includes support for multiple base layers, as well as for multiple in-die variation tables, including nested bias tables to account for reactive ion etching (RIE) and optical proximity correction (OPC) process variations during manufacturing. The Calibre xACT platform can also extract all parasitic capacitance components in an analog/RF design and generate a distributed RC netlist of the design that can be used in a downstream post-layout simulation flow. Inductance extraction (loop inductance and partial element equivalent circuit, or PEEC) accounts for high frequency skin effects during chip design and analysis.

Calibre xACT, xACT 3D, xRC, and xL processes all use TICER to reduce parasitic netlist size without affecting the accuracy of the netlist, and to speed up downstream simulation and analysis. The Calibre xACT platform functionality provides designers with a fast, highly accurate, and multi-purpose parasitic extraction tool with virtually unlimited design scope and fast, scalable performance convenient for analog/RF design characterization, enabling accurate post-layout simulation across a wide range of 5G designs and advanced process nodes.