기술 문서

Optimizing IC design verification: A customer success with the Calibre multiple job submission GUI

Screenshot of the Calibre Interactive GUI showing multiple job submissions.

As semiconductor designs grow increasingly complex, the need for automated, efficient verification workflows has become paramount. A global telecom leader leveraged Siemens EDA's Calibre Interactive Multiple Job Submission (MJS) GUI to transform their design verification process.

The Calibre MJS GUI enabled the customer to streamline the entire verification flow, automating job submissions, optimizing resource utilization, and providing comprehensive oversight to ensure no critical checks were missed. This resulted in improved efficiency, reduced risk of errors, and a more reliable sign-off process, empowering the customer's design teams to focus on innovation rather than verification overhead.

What you’ll learn:

  • How the Calibre Interactive Multiple Job Submission (MJS) GUI streamlines and automates the IC design verification workflow.
  • The key benefits the MJS GUI provides, including capturing the full verification flow, optimized layout streaming, enhanced status monitoring, and efficient license management.
  • The specific advantages the MJS GUI offers for block-level designers, such as templatized physical verification flows and an all-in-one sign-off platform.
  • How the adoption of the Calibre MJS GUI has resulted in improved efficiency, reduced complexity and a more reliable sign-off process for the customer's IC design teams.

Who should read this:

  • IC design engineers and CAD teams responsible for complex IC design verification and sign-off processes
  • Engineering managers and directors overseeing IC design and verification workflows
  • Design automation and tool selection decision-makers at semiconductor companies and design houses

공유

관련 자료

Korean Catapult High-Level Synthesis and Verification
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Korean Catapult High-Level Synthesis and Verification

Korean Verification (HLV) tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL.