기술 문서

Calibre 3DPERC: Your key to robust ESD solutions for 3D ICs

Diagram of a 3D integrated circuit showing stacked components: DRAM, HBM Controller, FPGA, MEMS, SoC-Chiplet 1, Chiplet 2, and Chiplet 3 on a Substrate, all with vertical interconnections.

As semiconductor designs move beyond the limits of planar integration, three-dimensional (3D) IC technology introduces new challenges for ESD (electrostatic discharge) protection and verification. In this paper, author Dina Medhat explores how traditional verification methods must evolve for 3D ICs, detailing the crucial differences in pad classification, protection circuit strategies and the impact of multi-die and multi-vendor assemblies.

The paper shares a proven workflow using Calibre 3DPERC, which has been developed to address the verification challenges that arise in advanced 3D and heterogeneous IC design. The tool supports automation of system-level ESD verification tasks and can handle chips assembled from multiple process nodes, foundries, and vendors. Its flexible rule system empowers ESD engineers to adapt methodology to meet specific project requirements, and its scalable design makes it suitable for large, complex assemblies. By enabling consistent and reliable ESD protection strategies, Calibre 3DPERC plays a critical educational and practical role in advancing IC reliability as 3D design adoption grows.

What you’ll learn:

  • How 3D IC architectures change ESD protection and verification requirements
  • The importance of IO pad classification in advanced multi-die designs
  • Practical methodology for efficient, automated 3D ESD verification using Calibre 3DPERC
  • Strategies to achieve system-level ESD reliability across multiple foundries and process technologies

Who should read this:

  • Reliability verification engineers
  • ESD design specialists
  • 3D IC designers
  • Engineering managers
  • Anyone involved in advanced semiconductor packaging, system integration or physical verification

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