사용이 간편하고 믿을 수 있는 디지털 설계 플로우를 사용한 IC 설계 부담 덜기

IROC Technologies는 제한된 내부 IC 설계 자원으로 처음부터 새롭게 IC를 설계해야 했습니다. 매우 촉박한 테이프아웃 일정을 맞추기 위해 IROC는 새 설계 플로우와 새 설계 소프트웨어를 사용해야 했습니다.

IROC’s Digital IC Design Flow Challenge

IROC needed to minimize digital IC design flow to meet the tapeout
schedule and shift to testing phases of the project. The place and route
(P&R) stage of IC design is particularly challenging as aggressive
Performance, Power and Area (PPA) targets compete for design priority.
Traditional P&R tools require significant user experience and
trial-and-error methodologies. Aprisa uses an innovative, differentiated
detailed-route-centric P&R architecture to ensure tight correlation from
pre-route to final post-route stages.

Digital IC Design Flow Software Requirements

With a compressed schedule, IROC needed a digital IC design flow software
that met their requirements, particularly minimizing risk. To finish the chip
on time, they needed an advanced node digital design flow that had a fast
time-to-tapeout. Other requirements included:

• High quality-of-results
• Reliable partnership and support
• Easy to set up and use
• Integrates well with other tools
• Excellent signoff correlation
• Validated for TSMC N16