Xpedition Package Designer (xPD)
Complete, powerful, and proven design solution for all forms of advanced semiconductor packaging technology
Xpedition Package Designer supports single- and multi-die/chiplet configurations and a variety of attachment technologies including wire bond, flip-chip, stacked-die, system-in-package (SiP) and package-on-package (PoP). It also supports the latest silicon-based technologies, such as RDL based fan-out wafer level packaging (FOWLP) and 2.5D/3D interposers including embedded and raised silicon bridges without requiring costly product add-ons or upgrades.
Benefits and features
- Supports design of advanced semiconductor packaging such as FOWLP, 2.5D/3D, heterogeneous integration using silicon, glass or organic interposers, embedded or raised substrate bridges, ABF build-up, RDL build-up, system-in-package and modules
- Advanced dynamic metal fill with DFM-ready results including multi-pass degassing, metal balancing and offset hatched planes
- Provides fast predictable design through real-time design visualization and editing in 2D and 3D
Removes/reduces time-consuming, post-design, signoff-driven ECOs through in-design geometry DRC - Direct creation of SI/PI 3D simulation models with the integrated Fast 3D field solver
Fast high quality mask generation using GDSII and OASIS - Shortest path and cycle time to full mask LVS and package assembly signoff through direct integration with Calibre 3DSTACK
Download the brochure to learn more.
관련 자료
Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.
Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.
STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.
High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?
Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.
Alibaba: Innovating Agile Hardware Development with Catapult HLS
At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.