Verifying SRAM yield inclusive of rare and random defects leveraging Solido Design Environment’s AI-powered methodology

Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone.

Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell.

This white paper presents a novel method to enable the inclusion of such rare and random defects into yield prediction frameworks.
Solido Design Environment (Solido DE) has been utilized to demonstrate that the bit-fail counts predicted using the proposed novel method match closely with the silicon data