Heterogeneous chiplet design and integration: bringing a new twist to SiP design

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which have hit the limits of physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, or chiplets, that typically include just a couple of functions, resulting in a multi-die heterogeneous integrated implementation.

Heterogeneous chiplet design, not yesterday’s SiP

This paper reviews five areas that have the most impact on successful implementation and design with chiplets including:

• Understanding what a chiplet design kit is and how it encompasses interface protocols, IO models, ATE test methods, power characteristics, and thermal models such as BCI-ROM
• How creating a digital twin drives all downstream aspects of design, analysis, and verification
• Using physical verification at every level of 3D assembly, from the substrate layer through design rule checks to assembly-level layout-versus-schematic.
• Multi-domain testing starting with the individual die and continuing with die-to-die and across the entire package assembly.
• Ecosystem interoperability including the ability to seamlessly share designs and data with suppliers, partners, foundries, and OSATs.

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