2024 Wilson Research Group IC/ASIC functional verification trend report

The 2024 Wilson Research Group Functional Verification Study provides an in-depth analysis of trends in IC/ASIC functional verification. The findings reveal the mounting challenges of verifying increasingly complex designs, driven by the rise of SoC-class architectures, security, safety-critical requirements and asynchronous clock domains. Alarmingly, first-silicon success rates have declined to their lowest level in two decades, with only 14 percent of projects achieving this milestone. To mitigate these challenges, the study highlights the growing adoption of advanced methodologies, including SystemVerilog, UVM and formal verification techniques. This report underscores the critical need for connected, data-driven and scalable verification solutions to address the industry’s rapid evolution and concerns about the talent gap in design and verification engineering.

Contents

I. Introduction

A. The global IC/ASIC semiconductor market

B. Study background

C. Study confidence interval

D. Study bias

E. Report organization

II. IC/ASIC verification effectiveness

A. Required spins

B. Types of flaws resulting in respins

C. Design completion compared to original schedule

III. IC/ASIC verification effort

A. Percentage of project time spent in verification

B. Mean peak number of engineers

IV. IC/ASIC design trends

A. Embedded processor cores

B. Asynchronous clock domains

C. Security features

V. IC/ASIC verification adoption trends

A. Verification languages and methodology adoption trends

B. Verification technology adoption trends

VI. Emulation and FPGA prototyping

VII. Conclusion