Equivalence Checking for FPGA

Systematic design errors introduced by synthesis or automated design refinement tools, or Trojan logic inserted by malicious actors, can be hard to detect and damaging if they make it into the final device. Using formal equivalence checking technology that has been used for ASIC design flows for many years, FPGA engineers can now exhaustively verify critical system components in their register transfer level (RTL) code to synthesized netlists and the final placed-and-routed FPGA designs, using an automated flow that is tightly integrated into the FPGA vendors’ platforms.

The Equivalence Checking for FPGA on-demand recording session will:

• outline the differences between formal verification and simulation in the context of equivalence checking
• define the verification challenges for sequential optimizations
• discuss the advantages of a step netlist verification approach and related applications
• present further related tasks that can be targeted using an equivalence checking verification flow

What You Will Learn:

• The need of equivalence checking for FPGAs
• Methodologies to apply equivalence checking
• The advantages and challenges of stepwise netlist verification

Who Should Attend:

• Design & Verification Engineers & Managers