AMD: Accelerating chip level DRC analysis with Calibre AI guided Engine

This session from User2User 2025 presents AMD's experience using a new Calibre chip level results analysis engine in place of traditional ASCII based chip debug methodologies.

Chip integration has become a major bottleneck, with design teams drowning in a sea of millions of design violations. Traditional debug tools simply can't keep up, forcing engineers to waste hours sifting through the chaos. With lightning-fast loading and intelligent violation clustering powered by advanced AI/ML, the tool gives you the control and clarity you need to triage problems like a pro. It accelerates chip level DRC analysis with “Signals” guided root-cause analysis.

In this talk, we will describe the details of this approach and present a demonstrative result using a reference design.