3D IC Test challenges, trends, and solutions

The Tessent 3D IC test approach is based on hierarchical DFT, SSN (Streaming Scan Network), enhanced TAPs (test access ports), and IEEE 1687 IJTAG (internal joint test action group) network technologies, all of which are IEEE 1838 compliant. Designed for scalability, flexibility, and ease-of-use, the Tessent solution helps customers optimize resources associated with IC test technology.

Testing 2.5D and 3D designs

The increasing number of 2.5D and 3D devices shows that is not just a contemporary
fashion but an important future direction of the semiconductor industry. 2.5D, in which multiple ICs are packaged side-by-side on a common interposer, and 3D, with dies and interposer stacked on top of each other, present unique challenges for IC test.

Only partial solutions exist today for the DFT and many details—including the DFT requirements—are not yet fully understood. There has, however, been progress throughout the semiconductor ecosystem in bringing the promise of 3D ICs to the mainstream of
design.