技術文献
Reduce time to tapeout with native IP block visualization in a full-chip context
Significantly reduce the time and effort needed to visualize and analyze IP within a full-chip context of the IC design layout during chip integration
When an SoC and its component blocks are developed simultaneously, the Calibre DESIGNrev chip finishing platform enables IP designers to visualize all instances of their block within the context of the full-chip layout without having to load the entire design multiple times in-memory, simplifying and speeding up the DRC analysis process for block owners. Enabling block owners to quickly see their blocks in context before actual implementation reduces the time required to confirm the IP meets the overall design specifications and requirements, speeding up the overall design flow while ensuring the SoC satisfies its design goals.