Automated and context-aware latch-up checking with the Calibre PERC reliability platform

One of the biggest challenges for circuit designers and verification engineers is identifying and eliminating unintentional failure mechanisms formed by inadvertent combinations of geometry and circuitry. Increases in design complexity, larger pin counts, and more power domains all contribute to the difficulty, as do the selection of process node and foundry that will host your next design. Understanding both the unintentional devices within your design and how the layout impacts critical distances of specific latch-up susceptible structures is critical. Automated context- and voltage-aware latch-up checking with the Calibre PERC reliability platform offers the fidelity and context required to fully identify latch-up susceptible regions in today’s dense, complex designs.

Latch-up detection and prevention is critical to ensure IC design performance and reliability.

Latch-up in IC designs often leads to chip failure. Traditional geometric design rule checks (DRC) solutions lack the context and voltage awareness needed to help designers find and eliminate latch-up conditions within designs. The Calibre PERC reliability verification platform provides advanced net analysis in conjunction with layout topology. This ability to consider both netlist and layout (GDS/OASIS) information simultaneously enables the tool to perform complex electrical checks that require both layout-related parameters and circuitry-dependent checks, such as voltage-aware net checking. With this functionality, the Calibre PERC platform helps designers reduce latch-up to ensure their chips deliver the performance and lifecycle for which they were designed.