Accelerate time to market with Calibre nmLVS Recon technology, a new paradigm for circuit verification
One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative shift-left early-stage design verification technologies, the Calibre nmLVS Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market.
Improve LVS circuit verification productivity in early-stage SoC integration and reduce time to market
To meet aggressive market schedules, SoC designers must often rush to start their chip integration before individual blocks are complete or even available. Designs containing gross systemic violations (such as shorted nets) not only generate thousands of error results, but also degrade the runtime and scalability of a full LVS iteration. The Calibre nmLVS Recon solution provides early-stage circuit verification to execute only those checks required to solve the highest-priority issues.
Engineers can easily toggle between different configurations, and decide which issue(s) they want to focus on in every round of execution. The Calibre nmLVS Recon process automatically determines which circuit verification requirements must be executed for maximum efficiency. Design teams can use the Calibre nmLVS Recon process to interactively and iteratively find and fix these types of violations quickly and efficiently, until the design is ready for full-chip signoff LVS iterations. The Calibre nmLVS Recon technology not only radically accelerates the overall circuit verification checking process, but provides a multi-configuration framework that further reduces verification TAT and time to market.