One of the biggest semiconductor engineering challenges today is delivering best-in-class devices while dealing with the technology scaling and cost limitations of monolithic IC design processes. To overcome these challenges, more companies are turning to heterogeneous integration and the 3D stacking of ICs and specialized chiplets (implemented in different processes geometries) into 3D ICs. Chiplets are small ICs specifically designed and optimized for operation within a package in conjunction with other chiplets and full-sized ICs. In heterogeneous designs, chips and chiplets are stacked and interconnected with vertical wiring. Designers can also combine them with 3D memory stacks, such as high bandwidth memory, on a silicon interposer within the package of a device.
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Companies wanting to lead the way in 3D heterogenous integrated design must adopt four enabling approaches:
Learn how to use the Siemens heterogeneous 3D IC solution to create designs that meet or exceed your PPA goals and improve the differentiation, profitability and time to market of your next market-leading project.
The Siemens 3D IC heterogeneous package workflow catapults you into the future of IC design today, with: