STMicro presents a unified way to integrate the definition of RTL and C
functional coverage and assertion (reducing the coding effort) and a method to
add constraints to the random values generated in UVMF.
CEA presents a methodology that bridges the open-source DL framework N2D2 and
Catapult HLS to help reducing the design process of hardware accelerators,
making it possible to keep pace with new AI algorithms.
Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to
RTL. In the RTL Design space, we will cover our technology for Power
Optimization with PowerPro Designer & Optimizer.
At the IP level, an ISP was created within a year using Catapult, a task
impossible using traditional RTL. To reduce dependency on designer experience,
Alibaba introduced an AI-assisted DSE tool.
Space Codesign Seminar: design flow including HW/SW co-design & HLS that allows
developers to migrate compute intensive functions from software running on an
embedded processor to a hardware based accelerator.
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