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Semiconductor Engineering Article: Preparing for 3D ICs

EDA experts on 3D IC chiplet tool and design workflow solutions

3D IC often seems daunting for design teams. Determining what to consider and when in the design workflow is a challenge with multiple chiplets. In this article, Semiconductor Engineering interviewed industry experts to learn more about preparing for 3D ICs and their impact on current tools and workflows.

See how experts answer:

  • How does 3D IC change various processes in the design flow?

  • What physical effects need consideration?

  • How do you consider the impact of other chips and chiplets in the design?

  • How do you manage variation margins?

    • More than Moore limitations: preparing for 3D ICs

    To prepare for challenges stemming from more than Moore limitations, designers need new methodologies such as 2.5D and 3D IC to meet market demands. The more features and more complex the electronic circuit design, the more processing capability is required. When designers face limitations with what’s available, they can use 2.5D or 3D IC to extend their capabilities. To do so, teams need to re-evaluate their design processes for 3D IC readiness.

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