Virage Logic: Memory power reduction in SoC designs using PowerPro MG

In this paper, we survey the key memory power reduction techniques available in memories designed for 40 and 32 nm process nodes from Virage Logic. We will show how PowerPro MG can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories.