Use advanced DFT and silicon bring-up to accelerate AI chip design

The market for AI chips is growing quickly, with the 2022 revenue of $20B expected to grow to over $300B by 2030. To keep up with the demand and stay competitive, AI chip designers set aggressive time-to-market goals. Design teams looking for ways to shave significant time off chip development time can look to advanced DFT and silicon bring up techniques described in this paper, including hierarchical test with Tessent™ Streaming Scan Network, shifting-left with Tessent RTL Pro, chiplet integration with Tessent Multi-die, shared memory BIST bus with Tessent MemoryBIST and faster chip bring up with Tessent Silicon Insight. Leading AI semiconductor companies have already had success with Tessent DFT tools.