Optimizing Your SoC or ASIC to Design PCBs More Cost Effectively

Shrinking silicon process nodes and increasing memory demands are a nightmare for PCB design teams working with custom ASICs or SoCs on high-performance systems. Huge devices with challenging bump and package-ball net assignments must be integrated onto the PCB while overall system integrity is maintained and signal-layer count and overall PCB size stay within system and cost constraints.

This paper examines the relationship between PCB signal-to-ASIC/SoC pin assignment and a product’s profit margin and discusses ways to generate competitive advantages without incurring significant time or cost penalties.