DDR4 board design and signal integrity verification challenges

As the PCB industry continues its transition towards higher speeds, improved channel efficiency and reduced power consumption, despite the increasing prevalence of DDR5 within high speed designs, DDR4 design remains a mainstay within the industry. Its introduction of pseudo open drain drivers represented a significant change in power consumption which has continued throughout the industry's latest designs.

What you will learn

• The use of pseudo open drain drivers within a DDR4 system
• What its use means for power consumption and Vref levels for the receivers
• A DDR4 system design example
• The need for simulating with IBIS power aware models versus transistor level models for simultaneous switching noise characterization.

Discover how you can accelerate simulation time and still achieve an impressively accurate simulation of SSO jitter effects.

This paper was presented at DesignCon, January 29, 2015. It is reproduced by permission.

To learn more, visit HyperLynx DDRx Design and Verification.