Covergate: coverage exposed

In the hardware verification world a common and popular technique for “checking” is to use coverage. Yet, as common and popular as it is, it is still the realm of the specialist or the verification IP. This paper will explore and simplify coverage through examples and use models. It will explore functional coverage, line coverage, expression coverage among others. It will explore coverage debug and coverage distribution. The examples offer a guide for simple, easy to use coverage models.

Automatically generated coverage

Coverage is a tool common in software design. The concept is easy to think about. If you have not “covered” something then you haven’t tested it. For example, a line of software that has never been executed is not covered, and is not tested.

10 int *p;
11 int condition1 = 0;
12 if (condition1)
13 value = *p;

In the code above, the condition in the ‘if’ is never true. That means that the assignment statement on line 13 has never been tested. A code coverage tool would generate a report that line 13 is untested. In its simplest form, this is code coverage.

In hardware verification these same coverage concepts apply. But now there are many more things to be covered – not just line execution, but also, expression values, branches, toggles and functional coverage.

Some coverage is “built-in” to the language. This allows tools to calculate coverage automatically. No intervention is needed. For example, the hardware simulator can know which statements are executable, and can keep track of whether the statement has been executed or not as simulation progresses. At the end of simulation a report of coverage can be produced.