Affordable and comprehensive design for test of 3D stacking die devices

Developers of high-end semiconductor products that face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time.

How then, can designers manage DFT for 3D stacked die devices?

In this paper, we outline a path to scalable DFT solutions into the third dimension to deliver an affordable and comprehensive answer to this question.

3D stacking and packaging is the next big step for improving SiP tech

As design size and complexity continue to dramatically increase, we also see fewer I/Os available for 2D package test access. The result of fewer test IOs and larger die size is significant increase in demand for test generation compute resources. These factors further combine to stress coverage, yield, power, and interconnect testing requirements.

The next major step for improving system-in-package technology is 3D die stacking and packaging. While there are multiple methods of 3D die stacking, they share the common goals of using smaller, high-yield dies that are vertically stacked. This strategy can alleviate many of the test challenges for large 2D or 2.5D devices.

Design for test 3D stacking considerations

While die-level test remains essentially unchanged from the 2D world, what about die-to-die testing in a 3D stack? 3D stacking packages require die-to-die (D2D) interconnect testing and reruns of known-good-die (KGD) tests to check for defects post packaging and assembly.

Learn more about design for test solutions for 3D IC in this paper

This paper describes a detailed implementation of IEEE 1838-2019 design-for-test (DFT). A 3D DFT solution is, in many respects, an extension of a hierarchical DFT methodology, but with one more level of hierarchy to consider -- the stack level.