Learn how to generate and optimize FastXOR to deliver the best overall LVL runtime.
Layout vs. Layout compare is performed throughout the IC design process as validation checkpoints to ensure design data changes were not made on restricted layers. Calibre FastXOR provides a faster alternative to traditional LVL flows for design iterations. This video demonstrates how to generate and optimize FastXOR to deliver the best overall LVL runtime.
Our Calibre How-To video series is designed to provide quick and easy solutions to your common problems and questions. The Calibre product suite integrates with all major EDA design tools you use in your IC design flow.