Video
Equivalence Checking for FPGA
Featuring OneSpin 360 EC-FPGA
Tempo di visione stimato: {minutes} minuti
The Equivalence Checking for FPGA on-demand recording session will:
outline the differences between formal verification and simulation in the context of equivalence checking
define the verification challenges for sequential optimizations
discuss the advantages of a step netlist verification approach and related applications
present further related tasks that can be targeted using an equivalence checking verification flow
What You Will Learn:
The need of equivalence checking for FPGAs
Methodologies to apply equivalence checking
The advantages and challenges of stepwise netlist verification
Who Should Attend:
Design & Verification Engineers & Managers