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DFT for tile-based designs
Mastering test for tiled designs
Tile-based IC design flows are predominant in today’s chips. A tiling style affects design-for-test (DFT) and calls for special attention to handling how scan channels are distributed across tiles. Tessent products can support tile-based designs from boundary scan, IJTAG and memory built-in self-repair (BISR) chain routing, bus-based packetized test delivery, and scan retargeting.