Data handling for D2D verification at the physical level

Chiplet systems are currently being discussed as a future solution for system integration. In a chiplet system, both the chip and the substrate must be designed, and there is a significant dependency between the two components. The parasitics of the substrate, for example, have a major impact on the power consumption and performance of the D2D interface. Therefore, in this presentation, a design flow will be introduced that allows design data from various sources to be merged into a complete system. The focus will be on linking data from the PCB and circuit world. This includes data in ODB+ format as well as OASIS or GDSII data from the chip world. With this data, comprehensive simulations of parasitic behavior can be performed.