Arm Zena-CSS running on Veloce proFPGA CS

Arm Zena‑CSS is a standardized, pre‑integrated compute subsystem validated on Siemens’ Veloce proFPGA CS platforms, enabling faster, lower‑risk automotive SoC development through cycle‑accurate FPGA prototyping, advanced memory and I/O modeling, and scalable infrastructure—at the cost of significant compute and operational overhead that must be actively managed.

In this session, Arm share how Zena‑CSS was validated using large‑scale FPGA prototyping on Siemens Veloce proFPGA CS platform—from early IP validation through full CSS‑level bring‑up. Attendees will learn how cycle‑accurate prototyping enabled rapid hardware/software co‑development, while also addressing the operational and compute‑cost challenges of prototyping at scale. The talk highlights both technical enablers and lessons learned from deploying Zena‑CSS on a multi‑FPGA, remotely operated prototyping infrastructure.