This video is the presentation of a paper published at the 2020 IEEE VLSI Test Symposium, which won the Best Paper award. Hear Janusz Rajski describe an innovative layout-friendly decompressor design used in the Tessent EDT (embedded deterministic test) architecture on which Tessent TestKompress operates. The new decompressor design is proven to significantly reduce the routing congestion associated with the decompressor circuitry on large industrial designs compared to traditional approaches. This makes it easier to use Tessent TestKompress with very high compression ratios on large, complex designs.