Microchip sees significant productivity gains in mature node custom IC design with in-design signoff DRC

Microsemi pioneered the design of innovative chips that are used for multiple purposes across a variety of industries, using both mature and advanced process nodes. In mature node custom design implementation, layout designers still spend a significant amount of their valuable time fixing DRC errors—time that could be more beneficially spent ensuring their designs meet their PPA goals. By replacing their intermediate batch DRC runs with the immediate signoff-quality DRC feedback provided by the Calibre RealTime Custom interface in custom layout editing and viewing environments, Microsemi designers not only improved their overall DRC productivity by 2-4X, but they were also able to simultaneously improve the quality of their layouts by implementing more edits to optimize their design PPA.