Reducing IC design effort with easy-to-use reliable digital IC design flow

IROC Technologies faced developing an integrated circuit (IC) - from scratch - with limited internal IC design resources. To meet the aggressive tapeout schedule, IROC needed to feel confident in the new design flow and software.

There's little flexibility for errors in mission-critical applications such as in aerospace. The IC would act as a test vehicle for a slew of testing, so getting a quality chip without many iterations would speed the overall project.

View the infographic to see how IROC Technologies leveraged a new place-and-route tool to tapeout an SoC in three months.

IROC’s Digital IC Design Flow Challenge

IROC needed to minimize digital IC design flow to meet the tapeout
schedule and shift to testing phases of the project. The place and route
(P&R) stage of IC design is particularly challenging as aggressive
Performance, Power and Area (PPA) targets compete for design priority.
Traditional P&R tools require significant user experience and
trial-and-error methodologies. Aprisa uses an innovative, differentiated
detailed-route-centric P&R architecture to ensure tight correlation from
pre-route to final post-route stages.

Digital IC Design Flow Software Requirements

With a compressed schedule, IROC needed a digital IC design flow software
that met their requirements, particularly minimizing risk. To finish the chip
on time, they needed an advanced node digital design flow that had a fast
time-to-tapeout. Other requirements included:

• High quality-of-results
• Reliable partnership and support
• Easy to set up and use
• Integrates well with other tools
• Excellent signoff correlation
• Validated for TSMC N16