Innovator3D IC brochure
Prototyping, planning and predictive analysis of heterogeneous integration platforms
Innovator3D IC delivers the fastest and most predictable path for planning and hetero- geneous integration of ASICs and chiplets using the latest semiconductor packaging 2.5D and 3D technology platforms and substrates.
Open architecture built around system technology co-optimization
Innovator3D IC is architected around the system technology co-optimization (STCO) methodology process developed by IMEC. STCO is utilized throughout prototyping and planning, design, sign-off, and manufacturing hand-off, concluding with comprehensive verification and reliability assessment.
Single digital twin data model of entire assembly
Innovator3D IC constructs and maintains a 3D digital
twin of the entire device including chiplets, interposers,
substrates, and even the system PCB.
Learn more by downloading this brochure
Learn more about the fill solution in our brochure including how Innovator3D IC delivers:
- Industry standards support
- Hierarchical device planning
- Chiplet to chiplet interface planning
- Predictive multiphysics analysis
- Comprehensive workflow support