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white paper

Avoiding configuration madness the easy way

A simpler, faster, easier to understand UVM configuration system

young man and young woman reading code on two monitors
The SystemVerilog UVM configuration system is widely used and poorly understood. A simpler more transparent system is proposed. It has desirable properties like being easy to read and easy to debug, with a simple implementation using a common base class for all settings. This new system supports setting values by name with a regular expression “scope” match, but eliminates the type-based matching. It is also significantly faster.

The UVM configuration database serves a useful purpose – to share data between the module/instance world and the dynamic class-based world in a UVM testbench. But it should be used sparingly.

If it cannot be used sparingly, then consider something easier to understand and simpler and faster. The package outlined here is about 300 lines and easy to understand. The UVM configuration database files contain about 2,600 lines of code and is not easy to understand.

The real hope for the reader is a realization that this is all “just code” and some things are better modeled other ways. Using bad habits with the UVM configuration database will eventually and naturally lead to changes – either a simple usage or a different implementation.

Three appendices chock full of coding tips are included in the paper.

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