2026 Functional Verification Study: Executive findings

This paper reveals an industry in which processor-rich and accelerator-class designs, software-driven behavior, safety and security requirements, and increasingly complex system interactions are reshaping functional verification. First-silicon success continues to decline, FPGA production bug escapes have risen, verification consumes roughly half of project time, and most projects are behind schedule. These outcomes should not be read as independent, causal claims. Taken together, the pattern suggests that risk increasingly arises from interactions among hardware, software, architecture, workloads, clocking and reset, power, safety, security, system operation as well as design errors.