Physical RTL Synthesis for Advanced Nodes with Oasys-RTL

High-level physical RTL synthesis is a critical step in the design implementation flow for improving the performance, power, and area of the design. Physical RTL synthesis tool, Oasys-RTL(tm), addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities. Oasys-RTL provides better quality of results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time. This whitepaper discusses the challenges of advanced node SoC/ASIC designs and how the Oasys-RTL physical RTL synthesis tool speeds turnaround time without degrading quality of results.