Optimizing HLS Code for Different FPGA Platforms

Digital logic solutions developers have a range of platforms they can choose from to implement their solution. The choice of platform could be simply choosing between ASIC or FPGA depending upon the potential market size or the stage of development.

This paper examines a simple convolution filter and outlines how it can be targeted using High-Level Synthesis (HLS) to different FPGA platforms. It will also focus on the different optimizations which might be needed to obtain the best performance when targeting different platforms, and coding styles that can be used to gain better performance.