Skip to Main Content
livre blanc

Optimizing curvilinear ILT recipe development with machine learning based pattern selection

Image shows Calibre SONR overview: machine learning based process aware layout analytics.
Inverse Lithography Technology (ILT) is key to moving the semiconductor industry beyond the 3nm design node, driven by design density and process window improvements. The test patterns used for recipe development play a critical role in achieving optimized ILT masks in terms of mask-friendliness, OPC convergence or multi-structure common focus range. The traditional way of test pattern selection is usually a clip-level manual search of design rules, which inevitably lacks critical design representations.

In this paper, we introduce Siemens EDA's Calibre SONR, a Machine Learning (ML) method to implement design layouts clustering and automatic pattern selections for ILT recipe tuning on a full-chip level. It is shown that SONR enables comprehensive coverage of the layout complicity and hence improves the robustness in the real full chip run. In addition, it improves productivity for recipe tuning without suffering any loss in the wafer performance by simulation in terms of EPE convergence, PVBand and common DOF.

Partager