IP Qualification with Oasys-RTL

With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. The Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualification platform to help designers create high-quality and physically implementable RTL.