Proposed standardization of chiplet models for heterogeneous integration

Innovative 2.5D and 3D IC packaging technology dramatically increases bandwidth and performance while also reducing power and cost of high-performance ASIC designs.

Separating typically single homogeneous, system-on-chip (SoC) ASIC device into different, unpackaged ASIC devices (chiplets) continues to gain traction. Function-specific chiplets are interconnected into a single heterogeneous integrated package (IP) with better performance at a reduced cost, higher yield and lower power.

Adoption requires industry standardizations to ensure compatibility between suppliers. Read the proposed set of standardized chiplet model paper by members of the Chiplet Design Exchange (CDX).

3D IC packaging challenges: integrating chiplet IP into SiP designs

While not all chiplets will require all models, the core set of deliverables supports design integration, verification and testing of the chiplet IP into a system in a package (SiP) design. Accounting for the integration, verification and testing is challenging because the workflows vary significantly from today's workflows.

Proposed standard chiplet models for heterogeneous integration authors

The authors of this paper are members of the Chiplet Design Exchange (CDX)— a working group under the Open Domain-Specific Architecture (ODSA) sub-project under the direction of the Open Compute Project Foundation (OCP). The CDX group consists of members from EDA vendors, chiplet providers, and SiP end users charted to recommend standardized chiplet machine-readable models and workflows to facilitate a chiplet ecosystem.

The need for chiplet models for heterogeneous integration

As general-purpose chiplet providers offer their devices for use in heterogeneous package designs, manufacturers need a standardized set of design models to ensure operability in electronic design automation (EDA) design workflows.

The proposal includes a set of standardized chiplet models that include thermal, physical, mechanical, IO, behavioral, power, signal and power integrity, electrical properties, and test models, as well as documentation to facilitate the integration of the chiplets into a design.

For successful industry-wide 3D IC packaging, these models should be:

• Electronically readable for use in design workflows
• Leverage existing industry standards that are readily available
• Compatible across the industry, without regard for supply for an open ecosystem and supply chain