Calibre PERC ESD flow and interactive usage for IP design

In this presentation from U2U North America 2024, Bryant Alvarez, Senior Physical Design Engineer at Intel, ​describes a shift-left methodology to optimize and verify electrostatic discharge (ESD) much earlier in the design cycle and speed up Calibre PERC ESD checks for IPs. Alvarez also shows how scalar methodologies and MTFLEX enablement in IP development allow optimization and verification with faster run times. Finally, Alvarez discusses the challenges and the methodology followed to verify and certify the ESD target for IP design and the Calibre PERC ESD flows (Topology, LDL, P2P, and CD) configuration needed for ESD verification in a foundry design.