Reduce cycle time in the post-tapeout flow
Every year, a staggering number of chip designs are delayed during the post-tape out flow, the final stage of IC design in which the design layout is converted into masks for manufacturing. Delays in getting the devices to market strongly impact revenue and profitability. A key factor in the delays is poor CPU utilization and scalability during the extremely compute-intensive post-tape out flow. Calibre FullScale directly reduces cycle time throughout the post-tape out flow by tackling two critical compute bottlenecks--data and operational dependency--by breaking compute tasks into smaller independent subtasks that can be run in parallel.
The FullScale integrated pipeline flow minimized IO overhead and optimized task scheduling with a combination of section-based and hierarch-based processing. Leading foundries are already seeing remarkable performance and scalability improvements in their post-tape out efficiency with Calibre FullScale.