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Compact modeling of stochastics and application in OPC

Failure rate distributions for the SRAM cell for three different OPC flavors. The onset of defectivity is lowered by more than an order of magnitude for stochastic OPC.

Managing stochastic variability is now crucial in advanced semiconductor manufacturing, especially with the adoption of EUV lithography. Traditional deterministic OPC methods struggle as process variability increases, but compact stochastic modeling provides a solution. This paper details Siemens and imec’s collaborative work in developing and validating a stochastic-aware OPC strategy, recently confirmed by imec’s wafer-level experiments, which were presented at 2025 Photomask Japan. The experimental results, consistent with earlier simulations, demonstrate dramatic reductions in stochastic failure probability across both repetitive SRAM and non-repetitive random logic layouts. This technical breakthrough enables more reliable defect reduction within state-of-the-art EUV process windows, reinforcing the effectiveness of Siemens’ next-generation OPC technology for industry-wide deployment.

This paper was originally published at the 2023 SPIE Advance Lithography + Patterning conference.

Werner Gillijns, Jae-uk Lee, Ryan Ryoung han Kim, Chih-I Wei, Xima Zhang, Azat Latypov, Germain Fenger, John Sturtevant, "Compact modeling of stochastics and application in OPC," Proc. SPIE 12494, Optical and EUV Nanolithography XXXVI, 124940J (28 April 2023); https://doi.org/10.1117/12.2658260

The paper that confirms wafer-level results was published by IMEC at the 2025 PMJ.

Renyang Meng, Xuelong Shi, Joost Bekaert, Werner Gillijns, and Ryoung-han Kim "Stochastic-aware compact OPC model validation for reducing failure probability", Proc. SPIE 13655, Photomask Japan 2025: XXXI Symposium on Photomask and Next-Generation Lithography Mask Technology, 1365507 (21 July 2025); https://doi.org/10.1117/12.3072074

What you’ll learn:

  • Why stochastic-aware OPC shows consistent defect reduction in both logic and SRAM EUV designs
  • The strengths of Siemens-imec collaboration in translating models from simulation to manufacturing
  • How balancing failure reduction and edge placement error delivers robust production strategies

Who should read this:

  • Semiconductor process and yield engineers
  • EUV lithography and OPC technologists
  • Memory and logic design teams targeting advanced nodes
  • R&D and technical leaders seeking proven, experimentally validated process control innovations

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