Glitch power estimation at SoC level using Veloce and PowerPro integrated flow

The rapid growth of high-performance computing (HPC) and AI workloads has pushed semiconductor design to unprecedented levels of complexity, making power consumption a critical concern. Among contributors to power usage, glitch power, spurious, nonfunctional signal transitions has emerged as a significant factor in AI and HPC SoCs, where sustained high-volume data movement and deep combinational logic amplify these effects. Traditional waveform-based and simulation methods struggle to capture glitch power accurately at scale, especially under realistic workloads, due to limited capacity, long turnaround times, and zero-delay assumptions in emulation.

This white paper introduces a scalable methodology integrating Siemens Veloce Strato CS emulation with PowerPro power estimation. By streaming real workload activity from the emulator into PowerPro, design teams can achieve accurate, delay-aware glitch power analysis across full-chip, large-scale SoCs. The flow leverages RTL and gate-level netlists, SDF, SPEF, and Liberty files, along with advanced partitioning and time-slicing strategies, to enable parallel processing and efficient power computation.

The approach allows designers to identify glitch-induced power hotspots early, evaluate the impact of process, voltage, and temperature variations, and optimize energy efficiency without compromising performance. Successfully deployed in customer environments, this integrated solution provides detailed cycle-accurate power insights, bridges the gap between zero-delay emulation and gate-level analysis, and supports energy-efficient design of modern AI accelerators and HPC SoCs.

By enabling precise, scalable, and practical glitch power estimation, this methodology empowers teams to design high-performance, energy-efficient SoCs and maintain a competitive edge in increasingly demanding computing markets.