Total recall: what to look for in a memory model library

The memory model library provides a comprehensive memory modeling solution and comes with an extensive range of configuration options that allow specific device parts or custom parts to be modeled very easily. The models come with built-in advanced verification features, can be used in any form of simulation-based verification environment, and are qualified to run on the Questa, Incisive, and VCS simulators.

Memory model library introduction

Almost all electronics systems use memory components, either for storing executable software or for storing data, therefore having accurate memory models available in proven, standards-based libraries is essential to the functional verification process. The models that make up the library should possess specific qualities, and the library itself should deliver a comprehensive solution that supports any type of simulation environment.

High fidelity memory models should include:

• Front door memory protocol interfaces
• Back door access
• Assertions
• Functional coverage monitors
• Memory protocol debug support
• Standards compliance
• Compatibility with all major simulators
• On-the-fly reconfiguration for second source evaluation

Siemens now offers a new, comprehensive memory Verification IP (VIP) library that embodies all of these qualities and addresses the growing need for accurate memory simulation models.

Memory model essentials

For verification modelling purposes a memory device can be abstracted as a signal-level protocol interface to a storage array. The signal-level interface has to conform to the timing and behavior of the memory protocol, which may be specified in an industry standard, such as the JEDEC JES79-3F standard for DDR3 or, in a specific case, it may be described in a device manufacturer’s datasheet. How the storage array is implemented is not directly visible to the user, but for simulation models it is generally implemented using either a SystemVerilog data structure or an optimized C data structure.

When a memory model is used in a testbench, it is instantiated as a component that is connected to a memory controller, which is either the design under test (DUT) or part of the DUT. Accesses to the memory take place using the signals of the memory model’s protocol front end, and data is transferred in and out of the model’s storage array. The complexity of the frontend protocol varies by memory type, but it can involve concurrent transfers interacting with a memory state space using control and status registers. Getting decent performance from some types of memory, such as DDR, relies on the controller recognizing certain types of data traffic and reorganizing the memory accesses to optimize the access rate in and out of memory. This level of sophistication requires a high fidelity memory model not only to reproduce the complex behavior and timing of a real memory device but also to determine whether the controller optimizations are effective.