Scalable reset domain crossing (RDC) verification using hierarchical data models
Requirements for accurate hierarchical RDC verification
RDC verification itself poses some unique challenges, because of which there is a need for hierarchical methodology dedicated to RDC verification. The proposed methodology should be able to accurately verify and detect following problems for an IPs and also for large scale integrated SoC:
Correctness of the Reset Tree
Reset usage in the design
* Do the asynchronous resets have synchronizers?
* Are there data paths crossing reset domains?
* Are the reset domain crossings metastability safe?
A SoC comprises of multiple IP level blocks which are developed and verified independently across multiple teams and geographies. Typically a SoC verification engineer integrates multiple IP blocks and focuses on the integration and issues in the top level. Block level verification is not required during SoC integrations as the blocks are already verified independently as part of the block level signoff. Hence, flat RDC verification on a SoC is redundant and time consuming. The requirement here is of a hierarchical methodology that can check for block integration issues and detect RDC issues across block level interfaces leading to faster RDC verification closure.