Optimal End-to-End DFT Automation with Tessent Platform

With the growth in design size and complexity, DFT engineers are adopting new methods to reduce DFT implementation time, reduce test costs, and reduce risks to design schedules by removing DFT from the critical path to tapeout. The primary method to accomplish large improvements to DFT efficiency is through a divide-and-conquer approach supported by Tessent’s RTL-based, hierarchical DFT insertion, validation, and pattern generation. Creating all the DFT at the core level then retargeting the core-level work to the chip-level has been widely proven to save time, save money, and reduce risk. Tessent Platform enables the most efficient hierarchical DFT flows.