From chaos to order

In recent years, continuous integration and development have become crucial in organizing software development cycles. As a result, it has also become a way to streamline the hardware flow, especially with the increased complexity of chips and SoCs. Integrating various teams that may be working on different systems, sub-systems, and IPs can be a challenge and may cause integration chaos. Continuous integration and development play an important role in organizing the hardware flow and making integration seamless, easy, and trackable, and with the ability to run multiple jobs in parallel, it is capable of accelerating the workflow. This paper discusses the ability of a hardware continuous integration flow to accelerate the functional verification flow and increase productivity and quality.

A continuous integration framework

A continuous integration flow enables engineering teams to parallelize the design and verification process. This paper presents a continuous integration architecture implementation aimed at enhancing hardware functional verification using static, formal, and simulation tools. The primary goal is to achieve close integration and supply essential metrics for verification tracking. This verification process can be applied at various points in the digital design flow, from the initial stages to sign-off. An optimized functional verification flow allows for the early detection of bugs, reducing the need for later adjustments.

EDA tools supporting continuous integration

With our proposed architecture, we successfully incorporated multiple tools into a single pipeline, including Lint, CDC, RDC, CDC protocol verification, CDC simulate effects, Sim CDC protocols/FX, and functional simulation. Achieving such an integrated process is complex, yet it allows for a seamless verification procedure and offers a visual representation of each step.

The paper presents the results of specific case studies from our end-users in the context of an AMBA DUT example. The results show a reduced analysis time using the same configuration to achieve a 2X reduction in total design time. Working up from the block level towards the top level also saves hardware verification engineers from “integration hell.”