Do not forget to “cover” your SystemC code with UVMC

We know how important coverage is in the verification cycle. But what if we are faced with a design that involves mixed languages like System Verilog (SV) and SystemC (SC) with UVM Connect (UVMC)? Do we collect functional coverage from SC models? Or do we ignore them and use coverage from the SV side in a verification environment?

This paper shares a novel approach to performing coverage on SystemC TLM transactions by exporting them to the SystemVerilog environment where we can make use of SystemVerilog covergroups. It also provides background on coverage analysis and SystemC modeling using UVMC, discusses the limitations of current methods, and uses examples to demonstrate the workflow and its results.