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Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis

Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis
Verification flow for testing RTL generated by HLS
Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.

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