In the presentation, we cover some of the AI design challenges faced with traditional tests. We will present options to solve them and our flow switching from traditional DFT solutions to future solutions, as we coop with the AI complexity and scale increase every generation.
DFT implementation has to be creative while dealing with design complexity size, power, quality, and design cycle while flow has to stay stable with minimum design and implementation flow changes. On top of it, DFT implementation had to face industry challenges at test targets in test time, test power, test equipment, etc.
Our current solution will show how we can keep up with the scale of future design roadmap and further increase design complexity and size. The presentation will examine the development process from chip DFT architecture, implementation challenges, and silicon results and will show the benefits of moving to an advanced solution and the results seen on silicon.